Multilevel Logic Synthesis for Cellular FPGAs Based on Orthogonal Expansions

The cellular ne grain architectures of new Field Programmable Gate Arrays FPGAs require spe cial logic synthesis tools Therefore this paper ad dresses multilevel logic synthesis methods based on or thogonal expansions for such kind of architectures First the concepts of the Binary Decision Diagrams BDDs their derivatives and the Functional De cision Diagrams FDDs which are applied to the technology mapping to Field Programmable Gate Ar rays FPGAs are generalized here to the Kronecker Functional Decision Diagram KFDD with negated edges Three other new types of functional decision diagrams are also introduced If Then Else KFDDs Mixed KFDDs and Permuted KFDDs The intro duced KFDD is based on three orthogonal Davio expansions and is created here also for multi output incompletely speci ed Boolean functions Next the KFDD creating algorithm being a basis of heuristic mapping program to ATMEL cellular FPGAs is also presented Besides this application our algorithm was adopted for technology mapping to Multiplexer Based MB and Table Look Up TLU based archi tectures